Patent Number: 6,310,399

Title: Semiconductor memory configuration with a bit-line twist

Abstract: A semiconductor memory configuration includes bit lines in a bit-line plane, a further plane different from the bit-line plane, word lines, and a memory cell area adjacent the bit-line plane, some of the bit lines having a twist running alongside others of the bit lines being untwisted, pairs of the some of the bit lines with a twist each respectively defining a twist bit-line pair, the twist bit-line pair having contacts for crossing one bit line of the twist bit-line pair over another bit line of the twist bit-line pair and over the memory-cell area through the further plane, the untwisted others of the bit lines having dummy contacts leading from the bit-line plane to the further plane. The dummy contacts lead to the word-line plane to give the word lines a homogeneous environment. The further plane can be a word-line plane including the word lines. The bit lines in the twist-free area can be approximately from 150 nm to 250 nm wide, preferably 200 nm. The twist area can only include the twist of the bit lines. The bit lines in the twist area can be approximately from 250 nm to 350 nm wide, preferably, 330 nm wide. The bit lines can have spacing from 150 to 180 nm wide. The bit lines, the word lines, the contacts, and the dummy contacts can be made from copper or aluminum.

Inventors: Feurle; Robert (Neubiberg, DE), Mandel; Sabine (Munchen, DE), Savignac; Dominique (Ismaning, DE), Schneider; Helmut (Munchen, DE)

Assignee: Infineon Technologies AG

International Classification: H01L 23/52 (20060101); H01L 21/70 (20060101); H01L 23/522 (20060101); H01L 27/108 (20060101); H01L 21/8242 (20060101); H01L 023/48 ()

Expiration Date: 10/30/2018