Patent Number: 6,310,467

Title: LDO regulator with thermal shutdown system and method

Abstract: A method and apparatus is directed to a thermal shut down for a low drop out (LDO) regulator including a MOS transistor. An error amplifier controls the gate of the MOS transistor by comparing the regulator output voltage to a reference voltage that is generated by a reference circuit. To enhance power supply rejection and improve regulation, the error amplifier and the reference circuits are powered by a potential at an internal power supply node. A power control circuit selectively couples the internal power supply node to one of the regulated output voltage and the unregulated supply voltage. A start-up circuit may be employed to ensure that regulation begins when power is applied. A temperature sensor circuit detects when the operating temperature exceeds a predetermined temperature and activates a supply transfer circuit to couple the unregulated supply to the internal power supply node. After the internal power supply node reaches the unregulated power supply potential, a shutdown circuit deactivates the MOS transistor. A diode is coupled between the regulator output and the internal power supply node to prevent current flowing from the internal power supply node to the load when the over-temperature condition exists. A transistor mirror may be configured to couple the unregulated supply voltage to the internal power supply node when activated. The thermal characteristics of a transistors threshold voltage may be employed as a temperature sensor. Another transistor may deactivate the MOS transistor by coupling the gate of the MOS transistor to the unregulated supply voltage.

Inventors: Sauer; Don R. (San Jose, CA)

Assignee: National Semiconductor Corporation

International Classification: G05F 1/10 (20060101); G05F 1/575 (20060101); G05F 001/575 ()

Expiration Date: 10/30/2018