Patent Number: 6,310,485

Title: Integrated circuit device having a burn-in mode for which entry into andexit from can be controlled

Abstract: An integrated circuit structure and method provides a burn-in stress testmode that facilitates stress testing of an integrated circuit device in aburn-in oven. The integrated circuit structure and method is capable ofdisabling a time-out feature of an IC memory device during a stress testmode of the device in order to facilitate stress testing of the device ina burn-in oven. The integrated circuit structure provides for entry intothe burn-in stress test mode when a supply voltage supplied to theintegrated circuit device exceeds a predetermined voltage level and/or thetemperature of the integrated circuit device exceeds a predeterminedtemperature level.

Inventors: McClure; David Charles (Carrollton, TX)


International Classification:

Expiration Date: 10/32013