Patent Number: 6,310,486

Title: Integrated test cell

Abstract: A semiconductor tester is disclosed that is adapted for testing semiconductor devices disposed on a handling apparatus. The semiconductor tester includes a tester housing defining a self-supporting frame and formed with an externally accessible opening adapted for receiving the handling apparatus. A test controller is disposed within the housing and carried by the frame. Pin electronics including tester circuitry are responsive to the test controller and proximately coupled thereto and mounted to the frame. A docking apparatus is disposed above the opening and is adapted to couple the tester circuitry to the handling apparatus.

Inventors: Trevisan; David (San Jose, CA), Caradonna; Michael A. (Los Altos, CA), Trudeau; Paul (Sunnyvale, CA), Blagdan; Isreal (San Jose, CA), LeColst; A. E. (Moorpark, CA)

Assignee: Teradyne, Inc.

International Classification: G01R 31/28 (20060101); G01R 031/26 ()

Expiration Date: 10/30/2018