Patent Number: 6,310,491

Title: Sequential logic circuit with active and sleep modes

Abstract: A sequential logic circuit having active and sleep modes prevents stored information from being lost immediately after the transition from a sleep mode to an active mode. This sequential logic circuit includes a latch circuit having an input terminal to which an input signal is applied, an output terminal from which and output signal is derived, and a set and/or reset terminal to which a set and/or reset signal is applied. The latch circuit has an active mode where a latch function is operable and a sleep mode where the latch function is inoperable, one of which is alternatively selected. The output signal is set or reset to have a specific logic state by the set or reset signal having a specific logic level applied to the set or reset terminal in the active mode. The sequential logic circuit further includes circuitry for preventing the set or reset signal from being applied to the set or reset terminal in the sleep mode, thereby avoiding loss of information or data latched in the latch circuit prior to transition to the sleep mode from the active mode. Thus, the information-latch operation in both of the modes is ensured.

Inventors: Ogawa; Tadahiko (Tokyo, JP)

Assignee: NEC Corporation

International Classification: H03K 3/037 (20060101); H03K 3/00 (20060101); H03K 3/012 (20060101); H03K 019/173 ()

Expiration Date: 10/30/2018