Patent Number: 6,310,492

Title: CMOS semiconductor integrated circuit

Abstract: In order to reduce power consumption, a power supply for a digital circuit portion is shut off, so that the output voltage of the power supply becomes the zero level. A CMOS (complementary metal oxide semiconductor) inverter has a P-channel FET (field effect transistor) with a gate electrode formed of P-type polysilicon. A source electrode of the P-channel FET is connected to the power supply and a back gate electrode of the P-channel FET is in direct connection with the aforesaid source electrode. The P-channel FET is placed in a state of not functioning as a transistor when the power supply is shut off in a low power consumption mode. However, in order to prevent the P-channel FET from undergoing characteristic degradation in that mode, there is the provision of a pull-down switch capable of fixing, in the mode, the voltage of the gate electrode of the P-channel FET at the zero level.

Inventors: Ikoma; Heiji (Nara, JP), Inagaki; Yoshitsugu (Osaka, JP), Konishi; Hiroyuki (Osaka, JP), Oka; Koji (Osaka, JP), Matsuzawa; Akira (Kyoto, JP)

Assignee: Matsushita Electric Industrial Co., Ltd.

International Classification: H03K 19/00 (20060101); H03K 19/003 (20060101); H03K 019/017 ()

Expiration Date: 10/30/2018