Patent Number: 6,310,495

Title: Clock wave noise reducer

Abstract: A clock circuit on an integrated circuit chip includes a driver having an output for deriving an output clock wave responsive to a clock wave of a clock wave source, a clock line having a first end coupled to the output of the driver, and a receiver having an input coupled to a second end of the clock line. The receiver has a resistive input impedance causing the clock line carrying the output clock wave to the input of the receiver to present to the driver output an impedance having a resistance-capacitance time constant that is a relatively small fraction of a period of the clock wave.

Inventors: Zhang; Johnny Q (San Jose, CA)

Assignee: Hewlett Packard Company

International Classification: H03K 5/003 (20060101); H04L 25/08 (20060101); G01R 019/00 ()

Expiration Date: 10/30/2018