Patent Number: 6,310,498

Title: Digital phase selection circuitry and method for reducing jitter

Abstract: In systems embodying the invention a voltage responsive circuit is used to generate a number of different clock signals having the same frequency, with each clock signal being delayed relative to any other clock signal by a certain delay which is a function of the amplitude of a control voltage applied to the voltage responsive circuit. The clock signals are multiplexed to enable any one of the different clock signals to be selected and to then be compared with a reference frequency signal for producing a gradually varying control voltage which is applied to the voltage responsive circuit. The different clock signals are suited for use in applications such as clock recovery and frequency synthesizer systems, where very little jitter is desired.

Inventors: Larsson; Patrik (Matawan, NJ)

Assignee: Agere Systems Guardian Corp.

International Classification: H03K 5/13 (20060101); H03L 7/099 (20060101); H03L 7/08 (20060101); H03L 7/18 (20060101); H03L 7/16 (20060101); H03L 7/089 (20060101); H04L 7/033 (20060101); H03L 007/00 (); H03K 005/00 ()

Expiration Date: 10/30/2018