Patent Number: 6,310,499

Title: Methods and apparatus for adjusting the deadtime between non-overlapping clock signals

Abstract: A clock gater circuit which may be easily tuned for the purpose of adjusting the deadtime between non-overlapping clock signals. The clock gater circuit has first and second clock inputs, a clock output, a falling clock edge generation circuit, and a rising clock edge generation circuit. The falling clock edge generation circuit is coupled between the first clock input and the clock output, and the rising clock edge generation circuit is coupled between the second clock input and the clock output. Each clock edge generation circuit has a feed-forward path and a feedback path. The feed-forward path of one of the clock edge generation circuits includes an inverter chain having an even number of inverters. If the inverter chain appears in the rising clock edge generation circuit, the inverter chain provides for easy adjustment of the rising edge of a clock produced by the gater circuit. However, an inverter chain which provides for easy adjustment of the timing of a clock edge may be provided in either or both of the clock edge generation circuits. When a clock gater circuit as described above is incorporated. into a system of clock gaters which produces a pair of non-overlapping clocks, the gater circuit can be used to easily adjust one or more deadtimes between the non-overlapping clocks.

Inventors: Radjassamy; Rajakrishnan (Plano, TX)

Assignee: Hewlett-Packard Company

International Classification: G06F 1/06 (20060101); H03K 5/15 (20060101); H03K 5/151 (20060101); H03K 003/017 ()

Expiration Date: 10/30/2018