Patent Number: 6,310,501

Title: Latch circuit for latching data at an edge of a clock signal

Abstract: A latch circuit comprises a delaying inverter circuit 1 for inverting a clock signal CLK with a predetermined delay, a precharge circuit for precharging a first node A and a second node B of the latch circuit to a predetermined potential during a time period in which the clock signal is in a first logic level, a first amplifier circuit for providing a potential difference between the first node A and the second node B in response to an input signal DIN during a first time period in which the clock signal CLK and an output signal iCLK of the delaying inverter circuit are in a second logic level, a second amplifier circuit for amplifying the potential difference between the first node and the second node during a time period in which the clock signal is in the second logic level and a flip-flop circuit adapted to be set and reset according to the potentials at the first and second nodes.

Inventors: Yamashita; Kazuo (Kanagawa, JP)

Assignee: NEC Corporation

International Classification: H03K 3/00 (20060101); H03K 3/356 (20060101); H03K 003/12 ()

Expiration Date: 10/30/2018