Patent Number: 6,310,505

Title: Semiconductor integrated circuit, delay-locked loop having the same circuit, self-synchronizing pipeline type system, voltage-controlled oscillator, and phase-locked loop

Abstract: The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a sense amplifier, a control input terminal is connected through a second capacitor to the input terminal of the sense amplifier, and a common connection point between the input terminal of the sense amplifier and the first and second capacitors is a floating node, and wherein a signal applied through the signal input terminal to the input terminal of the sense amplifier is vertically shifted by a control signal applied to the control input terminal, at least, near a determination threshold of the sense amplifier, thereby controlling a delay amount of an output.

Inventors: Ogawa; Katsuhisa (Machida, JP), Ohmi; Tadahiro (Sendai, JP), Shibata; Tadashi (Tokyo, JP)

Assignee: Canon Kabushiki Kaisha

International Classification: H03K 5/13 (20060101); H03L 7/099 (20060101); H03L 7/08 (20060101); H03L 7/081 (20060101); H03K 3/03 (20060101); H03K 3/00 (20060101); H03K 3/354 (20060101); H03K 5/00 (20060101); H03K 005/13 ()

Expiration Date: 10/30/2018