Patent Number: 6,310,506

Title: Programmable setup/hold time delay network

Abstract: A system and method for providing a programmable delay to an input signal in a device requiring setup and hold times for input signal, such as a DRAM device. In one embodiment, the programmable delay network 5 comprises a plurality of delay devices and at least one fuse connected between the input of the delay network 5 and the output of the delay network 5. Each fuse can connect in series with at least one delay device in such a manner that opening a fuse, or a combination of fuses, changes the amount of delay time the input signal experiences through the delay network.

Inventors: Brown; David R. (Sugar Land, TX)

Assignee: Texas Instruments Incorporated

International Classification: G11C 7/10 (20060101); H03K 5/13 (20060101); H03K 5/00 (20060101); H03H 011/26 ()

Expiration Date: 10/30/2018