Patent Number: 6,310,521

Title: Reference-free clock generation and data recovery PLL

Abstract: An apparatus comprising a first circuit, a second circuit, and a logic circuit. The first circuit may be configured to generate one or more first control signals having a first data rate in response to an input signal having a second data rate and a clock signal having the first data rate. The second circuit may be configured to generate one or more second control signals in response to the input signal and the clock signal. The first logic circuit may be configured to generate the clock signal in response to the one or more first control signals, the one or more second control signals and a third control signal.

Inventors: Dalmia; Kamal (Austin, TX)

Assignee: Cypress Semiconductor Corp.

International Classification: H03L 7/087 (20060101); H03L 7/08 (20060101); H03L 7/095 (20060101); H04L 7/033 (20060101); H03L 7/089 (20060101); H03L 007/087 ()

Expiration Date: 10/30/2018