Patent Number: 6,310,570

Title: System with adjustable ADC clock phase

Abstract: Analog to digital converters with enhanced performance in the presence of clock noise interference are configured with sampling clock phase selection circuitry to enable operation of the converter at the optimum sampling time intervals with respect to the interfering noise. The selection circuitry includes apparatus for generating a plurality of sampling clock phases and a multiplexer coupled to the plurality of phases to select the optimum clock phase.

Inventors: Rumreich; Mark Francis (Indianapolis, IN), Albean; David Lawrence (Indianapolis, IN), Gyurek; John William (Indianapolis, IN)

Assignee: Thomson Licensing S.A.

International Classification: H03M 1/08 (20060101); H03M 001/12 ()

Expiration Date: 10/30/2018