Patent Number: 6,310,669

Title: TFT substrate having connecting line connect to bus lines through different contact holes

Abstract: A TFT array substrate including: an insulating substrate, a gate electrode, a gate electrode line, an insulating film, a semiconductor layer, a contact layer, a source electrode, a drain electrode, a source electrode line, an interlayer insulating film, a pixel electrode, and a connecting line which is made of a same material that of the pixel electrode and connects electrically between the gate electrode line and the source electrode line through a second contact hole provided in the insulating film and a third contact hole provided in the interlayer insulating film.

Inventors: Kobayashi; Kazuhiro (Tokyo, JP), Nakamura; Nobuhiro (Kumamoto, JP), Endoh; Yukio (Kumamoto, JP)

Assignee: Mitsubishi Denki Kabushiki Kaisha

International Classification: G02F 1/13 (20060101); G02F 1/1362 (20060101); G02F 001/136 (); G02F 001/134 (); H01L 031/036 ()

Expiration Date: 10/30/2018