Patent Number: 6,310,795

Title: Semiconductor memory device with data retention characteristic of improved stability

Abstract: During standby, bit lines BL1 and /BL1 are precharged, and the potentials of word lines WL1 and WL2 are set at a potential slightly higher than a ground potential. Since a stable retaining current flows through an access transistor into a node inside a memory cell holding the H level, the data can be retained with stability. Moreover, during an access, the selected word line is brought to the H level, while the unselected word lines are brought to a ground potential.

Inventors: Morishima; Chikayoshi (Hyogo, JP)

Assignee: Mitsubishi Denki Kabushiki Kaisha

International Classification: G11C 11/412 (20060101); G11C 11/413 (20060101); G11C 005/06 ()

Expiration Date: 10/30/2018