Patent Number: 6,310,802

Title: Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts

Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

Inventors: Ma; Manny Kin F. (Boise, ID), Shirley; Brian (Boise, ID)

Assignee: Micron Technology, Inc.

International Classification: G11C 11/409 (20060101); G11C 11/4094 (20060101); G11C 29/04 (20060101); G11C 29/50 (20060101); G11C 29/02 (20060101); G11C 016/04 ()

Expiration Date: 10/30/2018