Patent Number: 6,310,805

Title: Architecture for a dual-bank page mode memory with redundancy

Abstract: A memory circuit (100) includes address circuitry (104) configured to receive address data and a plurality of I/O buffers (112). A core cell array (102) includes core cells and redundant core cells. Sense amplifiers (108) including read sense amplifiers (132) and redundant sense amplifiers may be coupled to the I/O buffers by word selection circuitry (110). Redundancy is implemented on an I/O-by-I/O basis, so that a redundant core cell and sense amplifier may be substituted for any failed bit in the core cell array.

Inventors: Kasa; Yasushi (Kawasaki, JP), Shing; Ming-Huei (Cupertino, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: G11C 7/00 (20060101); G11C 007/00 ()

Expiration Date: 10/30/2018