Patent Number: 6,310,806

Title: Semiconductor memory device with redundant circuit

Abstract: A redundant memory circuit stores a defective row address. A switch circuit connects a spare row decoder with the wire for transmitting a row address signal according to the defective row address stored in the redundant memory circuit when the power supply is turned on. A row decoder deactivating circuit, when the power supply is turned on, deactivates the part of the row decoder corresponding to the defective row address according to the defective row address stored in the redundant memory circuit. As a result, when the row address buffer outputs the row address signal corresponding to the defective row address, the spare row decoder decodes the row address signal, thereby selecting a spare word line immediately.

Inventors: Higashi; Tomoki (Kawasaki, JP), Nakano; Hiroaki (Yokohama, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G11C 29/00 (20060101); G11C 007/00 ()

Expiration Date: 10/30/2018