Patent Number: 6,310,807

Title: Semiconductor integrated circuit device including tester circuit for defective memory cell replacement

Abstract: Following data writing into a memory cell array according to an internal address signal, the data read out from each memory cell is compared with expected value data in a readout operation. A row decoder selects a plurality of memory cells belonging to the same row in the memory cell array at one time according to an address signal. A BIST circuit determines that repair is to be carried out with a spare memory cell row, not a spare memory cell column, when a plurality of defective memory cells are detected from the plurality of memory cells selected at one time.

Inventors: Ooishi; Tsukasa (Hyogo, JP), Hidaka; Hideto (Hyogo, JP)

Assignee: Mitsubishi Denki Kabushiki Kaisha

International Classification: G11C 29/04 (20060101); G11C 29/44 (20060101); G11C 29/00 (20060101); G11C 029/00 ()

Expiration Date: 10/30/2018