Patent Number: 6,310,809

Title: Adjustable pre-charge in a memory

Abstract: A memory device can read data stored in memory cells using a differential voltage sensing technique. The memory includes a differential voltage sensing circuit having two input nodes. The nodes of the sensing circuit are pre-charged prior to reading the memory cell. The nodes are pre-charged by charge sharing multiple bit lines. In one embodiment, local bit lines having a first charge are coupled to global bit lines having a second charge to provide a desired pre-charge level. The local and global bit lines can have equal capacitance values. The voltages of the bit lines prior to charge sharing can be any selected value, but in one embodiment the local bit lines are discharged to ground and the global bit lines are charged to Vcc. The memory includes a programmable fuse circuit to selectively activate pass circuitry and couple one or more local bit lines to a global bit line in response to the pass command code. This allows the pre-charge level of the sensing nodes to be adjusted after fabrication. Thus, fabrication variables can be offset and a bit line disturb condition avoided. The fuse circuit can include programmable non-volatile cells.

Inventors: Roohparvar; Frankie F. (Miltitas, CA), Nobunaga; Dean (Fremont, CA)

Assignee: Micron Technology, Inc.

International Classification: G11C 7/18 (20060101); G11C 7/00 (20060101); G11C 7/12 (20060101); G11C 16/24 (20060101); G11C 16/28 (20060101); G11C 16/06 (20060101); G11C 007/00 ()

Expiration Date: 10/30/2018