Patent Number: 6,310,811

Title: Memory with high speed reading operation using a switchable reference matrix ensuring charging speed

Abstract: A semiconductor memory device includes a memory cell matrix section, a reference memory cell matrix section and a sensing circuit. The memory cell matrix section includes memory cells arranged in a first matrix. When one of the memory cells is selected based on an address signal, a read data signal corresponding to a storage data of the selected memory cell is outputted. The reference memory cell matrix section includes reference memory cells arranged in a second matrix, and outputs a reference data signal for the read data signal from the selected memory cell. The sensing circuit senses the storage data based on the read data signal from the memory cell matrix section and the reference data signal from the reference memory cell matrix section. At this time, the reference memory cell matrix section outputs the reference data signal to the sensing circuit such that the reference data signal appears in substantially synchronous with the data read signal.

Inventors: Kohno; Takaki (Tokyo, JP)

Assignee: NEC Corporation

International Classification: G11C 16/04 (20060101); G11C 16/06 (20060101); G11C 7/00 (20060101); G11C 7/06 (20060101); G11C 7/14 (20060101); G11C 16/28 (20060101); G11C 007/02 ()

Expiration Date: 10/30/2018