Patent Number: 6,310,812

Title: Integrated memory having memory cells and reference cells

Abstract: Memory cells are arranged at crossover points of word lines WLi and bit lines. First reference cells are arranged at crossover points of at least one first reference word line and bit lines. In a normal operating mode, the reference cells serve for generating a reference potential on the bit lines prior to a readout of the memory cells. Second reference cells are arranged at crossover points of at least one second reference word line and the bit lines. In a test operating mode, the second reference cells serve for generating a reference potential on the bit lines prior to a readout of the reference cells.

Inventors: Pochmuller; Peter (Munchen, DE)

Assignee: Infineon Technologies AG

International Classification: G11C 11/22 (20060101); G11C 29/04 (20060101); G11C 29/24 (20060101); G11C 029/00 ()

Expiration Date: 10/30/2018