Patent Number: 6,310,815

Title: Multi-bank semiconductor memory device suitable for integration with logic

Abstract: Subbanks are arranged in four regions of a DRAM macro having a rectangular shape, bank control circuits are arranged in a prescribed region between these subbanks, and internal read/write data buses are arranged in a region different from the region where the bank control circuits are arranged. Since there is no crossing of the bank control circuits and the internal read/write data buses, the bank control circuits can be efficiently arranged to reduce the layout area. Accordingly, a semiconductor integrated circuit device including multi-bank memories which operates stably at high speed can be provided without increase of an area occupied by a chip.

Inventors: Yamagata; Tadato (Hyogo, JP), Yamazaki; Akira (Hyogo, JP), Tomishima; Shigeki (Hyogo, JP), Yukinari; Yoshio (Hyogo, JP), Hatakenaka; Makoto (Hyogo, JP), Miyanishi; Atsushi (Hyogo, JP)

Assignee: Mitsubishi Denki Kabushiki Kaisha

International Classification: G11C 8/12 (20060101); G11C 8/00 (20060101); G11C 5/14 (20060101); G11C 008/00 ()

Expiration Date: 10/30/2018