Patent Number: 6,310,817

Title: Multi-bank memory with word-line banking, bit-line banking and I/O multiplexing utilizing tilable interconnects

Abstract: A multiple bank memory array includes a combined memory array, an X-decoder, a first word-line driver, a second word-line driver, a reference column, a Y-muitiplexer and pre-chargingz circuit, a sense amplifier and input/output circuit, and control and pre-coding logic. Signals are received and applied to the combined memory array and the other components via the control and pre-decode logic and the input/output circuit. The control and pre-decode logic receives control signals to control and address the combined memory array, and uses a single bit for two dimensional decoding. This architecture for multiple bank memory cell arrays a novel technique for word-line banking using tillable strap cells in a first embodiment that provides a combined array, does not require routing and eliminates redundant reference columns. The multiple bank memory array in a second embodiment also includes a novel technique for bit-line banking that eliminates sense amplifiers, provides for tilable connection between the sense amplifiers and the input/output circuit, and maintains an optimum aspect ratio. In a third embodiment, the invention provides a tilable I/O interconnect structure for use on another level of banking. The banking concepts provided in the present invention are independent of the type of memory cell and applicable to all varieties of memory cells.

Inventors: Kablanian; Adam (San Jose, CA)

Assignee: Virage Logic Corporation

International Classification: G11C 5/02 (20060101); G11C 008/12 ()

Expiration Date: 10/30/2018