Patent Number: 6,310,819

Title: Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals

Abstract: A self refresh decoder generates a self refresh command as long as the clock enable signal transitions low within a predetermined latency period after an auto refresh command is generated. As a result, an SDRAM is able to enter the self refresh mode even though the clock enable control signal differentiating the auto refresh command from the self refresh command is excessively delayed beyond the other control signals corresponding to both the auto refresh and the self refresh commands. The self refresh decoder includes a counter that is preloaded with a latency value and decrements to a terminal count responsive to the auto refresh command to terminate the latency period. The output of the counter is decoded to provide an enable signal as long as the terminal count has not been reached. As long as the enable signal is present, the self refresh command is generated responsive to receipt of the clock enable signal.

Inventors: Cowles; Timothy B. (Boise, ID), Wright; Jeffrey P. (Boise, ID), Zheng; Hua (Fremont, CA)

Assignee: Micron Technology, Inc.

International Classification: G11C 11/406 (20060101); G11C 007/00 ()

Expiration Date: 10/30/2018