Patent Number: 6,310,820

Title: Relaxed write timing for a memory device

Abstract: A memory device provides a relaxed write timing scheme that improves access time. The address and/or the data is set up to the memory array during a previous write cycle so that the next write cycle can proceed without delays produced in delivering the address and/or the data to the array during the write cycle in which the data is to be written to the array.

Inventors: Porter; John D. (Meridian, ID), Thompson; William N. (Meridian, ID), Weber; Larren G. (Caldwell, ID)

Assignee: Micron Technology, Inc.

International Classification: G11C 7/22 (20060101); G11C 7/00 (20060101); G11C 008/00 ()

Expiration Date: 10/30/2018