Patent Number: 6,310,821

Title: Clock-synchronous semiconductor memory device and access method thereof

Abstract: A clock-synchronous semiconductor memory device includes many memory cellsarranged in matrix, a count section for counting the actual number ofcycles of a continuous, externally-supplied basic clock signal, a controlsection for inputting a row enable control signal (/RE) and the columnenable control signal (/CE) provided from an external device, other thanthe basic clock signal, for which the control signals are at a specifiedlevel, synchronized with the basic control signal, and for setting theinitial address for data access of the memory cells, and a data I/Osection for executing a data access operation for the address set by thecontrol section. In the device, the output of data from the memory cellsthrough the data I/O means is started after the setting of the initialaddress by the control sections and after a specified number of basicclock signals has been counted by the count section.

Inventors: Toda; Haruki (Kanagawa-ken, JP), Kuyama; Hitoshi (Kanagawa-ken, JP)


International Classification:

Expiration Date: 10/32013