Patent Number: 6,310,824

Title: Integrated memory with two burst operation types

Abstract: The memory has a bidirectional address counting unit C1; S, which performs a counting operation for the purpose of generating internal column addresses from an external column address A7 . . . 0. In this case, the counting direction is dependent on the burst operating mode and on an address bit A1 of the external column address. Moreover, the memory has a transformation unit C2; SR2, which forwards partial addresses A2 . . . 1'; PA3 . . . 0' generated by the address counting unit C1; S either unchanged or incremented by the value 1 to the second column decoder CDEC2, in a manner dependent on the burst operating mode and a further address bit A0 of the external column address A7 . . . 0.

Inventors: Schoniger; Sabine (Munchen, DE), Schrogmeier; Peter (Munchen, DE), Weis; Christian (Munchen, DE), Dietrich; Stefan (Turkenfeld, DE)

Assignee: Infineon Technologies AG

International Classification: G11C 7/10 (20060101); G11C 008/00 ()

Expiration Date: 10/30/2018