Patent Number: 6,310,826

Title: Semiconductor device having a test circuit

Abstract: A semiconductor memory device includes a memory circuit from which data is read in correspondence with a first reference clock signal. A multiplexer outputs the data read from the memory circuit in correspondence with the second reference clock signal. A comparison determination circuit receives the data read from the memory circuit via the multiplexer and compares the read data with an expected data value in correspondence with the second reference clock signal to generate determination result data.

Inventors: Koto; Tomohiko (Kasugai, JP)

Assignee: Fujitsu Limited

International Classification: G11C 29/04 (20060101); G11C 29/44 (20060101); G11C 29/38 (20060101); G11C 008/00 ()

Expiration Date: 10/30/2018