Patent Number: 6,310,874

Title: Learn pending frame throttle

Abstract: Flow of data units to an address resolution processor is controlled toinhibit multiple data units from a single multicast flow from beingenqueued with the address resolution processor. In a switch having aplurality of Input/Output Application Specific Integrated Circuits ("I/OASICs") with a plurality of ports, no more than one data unit from eachI/O ASIC is permitted to be enqueued with the address resolution processorat any point in time. A separate learn pending indicator may be definedfor each I/O ASIC in the switch.

Inventors: Miller; David S. (Framingham, MA), Boxer; Lawrence Aaron (Carlisle, MA), Heiner, Jr.; Edward A. (Londonderry, NH)


International Classification:

Expiration Date: 10/32013