Patent Number: 6,310,928

Title: PLL circuit

Abstract: A PLL circuit comprises a storage/control circuit for storing, in anassociated manner, a plurality of PLL output frequencies to be designated,lock ranges including the PLL output frequencies in their central regionsrespectively, and information on the number of stages of delay circuits.The number of stages of the delay circuits having a lock range including adesignated PLL output frequency in its central region is selected andcontrolled by the storage/control circuit. A frequency divider selects andcontrols a frequency division ratio for obtaining a PLL output frequencyon the basis of a frequency of a reference signal.

Inventors: Yunome; Takao (Yokohama, JP)


International Classification:

Expiration Date: 10/32013