Patent Number: 6,311,148

Title: Method for determining static flip-flop setup and hold times

Abstract: A method for determining the setup and hold times of static flip-flops during the design and development of integrated circuits. The method utilizes simulations of an integrated circuit to determine a first amount of time required for a data signal to be transmitted from a first external node to a predetermined node in the register of a static flip-flop, and a second amount of time required for a clock signal to be transmitted from a second external node to the predetermined node. The setup time is determined by calculating a difference between the first amount of time from the second amount of time. Similarly, a hold time for the flip-flop is determined by calculating a difference between the amounts of time required for data and the clock signal to reach a second predetermined internal node of the flip-flop.

Inventors: Krishnamoorthy; Suresh (Milpitas, CA)

Assignee: Sun Microsystems, Inc.

International Classification: G06F 17/50 (20060101); G06F 017/50 ()

Expiration Date: 10/30/2018