Patent Number: 6,311,239

Title: Architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media

Abstract: An architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media that may comprise a first circuit configured to present a first series of data packets having a first bit-width in response to a second series of data packets having a second bit-width and a second circuit configured to present a third series of data packets having said first bit-width in response to said second series of data packets. The first circuit may comprise a buffer circuit configured to hold one or more of the first series of data packets and a packer circuit configured to present the second series of data packets in response to the data packets held in the buffer circuit. The second circuit may comprise an unpacker circuit configured to present the third series of data packets and a buffer circuit configured to hold one or more of the third series of data packets.

Inventors: Matthews; Joe P. (Savage, MN)

Assignee: Cypress Semiconductor Corp.

International Classification: G06F 5/00 (20060101); H04Q 11/04 (20060101); H04Q 011/04 (); H04J 003/16 (); G06F 007/38 (); G06F 003/00 (); G06F 015/76 ()

Expiration Date: 10/30/2018