Patent Number: 6,311,248

Title: Method and system for optimized data transfers in a mixed 64-bit/32-bit PCI environment

Abstract: A method for optimizing the performance of a 64-bit PCI initiator when transferring a 64-bit data via a 64-bit PCI bus. The 64-bit PCI initiator receives a single 64-bit data for transfer via the 64-bit PCI bus. The 64-bit PCI initiator breaks the 64-bit data into a first 32-bit data and a second 32-bit data. The 64-bit initiator then initiates a data transaction with the target device arbitrating for ownership of the 64-bit PCI bus. Upon receiving ownership of the 64-bit PCI bus, the 64-bit PCI initiator transfers the first 32-bit data and then transfers the second 32-bit data to the target device via the 64-bit PCI bus. The first 32-bit data and the second 32-bit data are transferred by the 64-bit PCI initiator to the target device without the assertion of a REQ64# signal, such that a REQ64# ACK64# protocol is avoided, enabling a more efficient completion of the data transaction.

Inventors: Meiyappan; Subramanian S. (Tempe, AZ), Chambers; Peter (Phoenix, AZ)

Assignee: VLSI Technology, Inc.

International Classification: G06F 13/40 (20060101); G06F 013/14 (); G06F 013/364 ()

Expiration Date: 10/30/2018