Patent Number: 6,311,250

Title: Computer memory controller with self refresh performed during memory back-up operation in case of power failure

Abstract: A computer memory controller comprises a dynamic random access memory (DRAM) timing control section that provides, during memory back-up operation mode, self-refresh timing to a DRAM array having self-refresh function. The memory controller also comprises a refresh/back-up control section that provides information as to memory back-up state to the DRAM timing control section. A DRAM identification mode register is provided. When a DRAM array without a self-refresh function is mounted, the state of the register changes. The state of the register is fed to the DRAM timing control section, thereby to provide timing according to the conventional column address strobe (CAS) before row address strobe (RAS) or CBR refresh method to the DRAM array.

Inventors: Kishino; Tsuyoshi (Yamanashi, JP)

Assignee: NEC Corporation

International Classification: G11C 11/406 (20060101); G06F 012/16 (); G11C 011/406 ()

Expiration Date: 10/30/2018