Patent Number: 6,311,254

Title: Multiple store miss handling in a cache memory memory system

Abstract: A cache memory system including a cache memory suitable for coupling to a load/store unit of a CPU, a buffer unit comprised of a plurality of entries each including a data buffer and a corresponding address tag. The system is configured to initiate a data fetch transaction in response to a first store operation that misses in both the cache memory and the buffer unit, to allocate a first entry in the buffer unit, and to write the first store operation's data in the first entry's data buffer. The system is adapted to write data from at least one subsequent store operation into the first entry's data buffer if the subsequent store operation misses in the cache but hits in the first entry of the buffer unit prior to completion of the data fetch transaction. In this manner, the first entry's data buffer includes a composite of the first and subsequent store operations' data. Preferably, the cache system is further configured to merge, upon completion of the data fetch, the fetched data with the store operation data in the first entry's data buffer and to reload the cache memory from the first entry's data buffer. In the preferred embodiment, each buffer unit entry further includes data valid bits that indicate the validity of corresponding portions of the entry's data buffer. In this embodiment, the buffer unit is preferably configured to reload the cache memory from the first buffer unit entry if all of the first entry's data valid bits are set prior to completion of the data fetch transaction thereby affecting a "silent" reload of the cache memory in which no data is ultimately required from memory.

Inventors: Kuttanna; Belliappa Manavattira (Sunnyvale, CA), Patel; Rajesh (Austin, TX), Snyder; Michael Dean (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 12/08 (20060101); G06F 012/00 ()

Expiration Date: 10/30/2018