Patent Number: 6,311,255

Title: System and method for selectively restricting access to memory for bus attached unit IDs

Abstract: A method and apparatus for selectively restricting access to a shared memory is presented in a computer network system having at least one bus capable of attaching a plurality of units to a shared memory. A first adapter unit is attached to the bus initiating a first address on the bus to access the shared memory and the adapter unit establishes control over the bus. An ID circuit is also provided that is in processing communication with the adapter and the bus for associating an adapter address to a unit id, where the circuit id is capable of detecting when a first ID belongs to the first adapter that has been given control of said bus. A memory control unit is attached to the bus for utilizing the first address for accessing said shared memory. An address checker circuit is in processing communication with the bus and is provided. The checker circuit is capable of associating a second address with a second adapter ID. An error generator is also provided for comparing values of the first address and first adapter ID to the second adapter ID and address to one another which will generate an error indicator when the values agree.

Inventors: Sadana; Sumit (Poughkeepsie, NY)

Assignee: International Business Machines Corporation

International Classification: G06F 12/14 (20060101); G06F 13/362 (20060101); G06F 13/36 (20060101); G06F 012/14 ()

Expiration Date: 10/30/2018