Patent Number: 6,311,261

Title: Apparatus and method for improving superscalar processors

Abstract: The invention involves new microarchitecture apparatus and methods for superscalar microprocessors that support multi-instruction issue, decoupled dataflow scheduling, out-of-order execution, register renaming, multi-level speculative execution, and precise interrupts. These are the Distributed Instruction Queue (DIQ) and the Modified Reorder Buffer (MRB). The DIQ is a new distributed instruction shelving technique that is an alternative to the reservation station (RS) technique and offers a more efficient (improved performance/cost) implementation. The Modified Reorder Buffer (MRB) is an improved reorder buffer (RB) result shelving technique eliminates the slow and expensive prioritized associative lookup, shared global buses, and dummy branch entries (to reduce entry usage). The MRB has an associateive key unit which uses a unique associative key.

Inventors: Chamdani; Joseph I. (Marietta, GA), Alford; Cecil O. (Lawrenceville, GA)

Assignee: Georgia Tech Research Corporation

International Classification: G06F 9/38 (20060101); G06F 009/38 ()

Expiration Date: 10/30/2018