Patent Number: 6,311,264

Title: Digital signal processor with wait state register

Abstract: A data processing device is used with peripheral devices having addresseesand differing communication response periods. The data processing deviceincludes a digital processor adapted for selecting different ones of theperipheral devices by asserting addresses of each selected peripheraldevice. Addressable programmable registers hold wait state valuesrepresentative of distinct numbers of wait states corresponding todifferent address ranges. Circuitry responsive to an asserted address tothe peripheral devices asserted by the digital processor generates thenumber of wait states represented by the value held in one of theaddressable programmable registers corresponding to the one of the addressranges in which the asserted address occurs, thereby accommodating thediffering communication response periods of the peripheral devices.

Inventors: Boutaud; Frederic (Roquefort les Pins, FR), Ehlig; Peter N. (Houston, TX)


International Classification:

Expiration Date: 10/32013