Patent Number: 6,311,267

Title: Just-in-time register renaming technique

Abstract: A target register of an instruction is assigned a rename register in response to the instruction being issued. That is, the target register is renamed at issue time, not at dispatch time. To handle a new deadlock issue this gives rise to, rename register allocation/deallocation logic, according to the present invention, includes logic for allocating and deallocating two sets of rename registers, one set from a regular rename buffer and another set from an overflow rename buffer. According to this allocation/deallocation logic, if the oldest dispatched, noncompleted instruction is ready for assignment of a rename register and the regular rename buffer is full, then a rename register is assigned from the overflow rename buffer to this instruction.

Inventors: Nguyen; Dung Quoc (Austin, TX), Le; Hung Qui (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 9/38 (20060101); G06F 009/38 ()

Expiration Date: 10/30/2018