Patent Number: 6,311,280

Title: Low-power memory system with incorporated vector processing

Abstract: A battery-powered portable radio device saves on the overall power consumed by the whole device by skipping unnecessary read, write, and refresh cycles of the internal main memory DRAM core. Streaming data input from a radio receiver is analyzed by a vector processor. The DRAM main memory and the vector processor itself share real estate on a common semiconductor chip. This allows a very wide row of DRAM memory to communicate 1024 bits wide with an eight-line cache. Six lines of the cache are reserved for memory operations, and two lines are reversed for I/O operations. Streaming data from the radio receiver is stored up in the DRAM main memory via the two I/O cache lines. As raw data is needed by the vector processor, whole DRAM rows are downloaded to the six lines of memory cache. The single-instruction multiple data vector processor rolls intermediate data around through the cache without causing it to write back to the DRAM. Any lines in the cache that will never be needed again, or that will be overwritten, are not written back. Any rows of data in the DRAM that will never be read or that will be overwritten are not refreshed. Each skipped read, write, or refresh of a row in the DRAM main memory saves significant battery power overall.

Inventors: Vishin; Sanjay (Sunnyvale, CA)

Assignee: nBand Communications

International Classification: G06F 12/08 (20060101); G06F 15/78 (20060101); G06F 15/76 (20060101); G06F 001/26 ()

Expiration Date: 10/30/2018