Patent Number: 6,311,292

Title: Circuit, architecture and method for analyzing the operation of a digital processing system

Abstract: A dual access debugging architecture. This architecture allows the microprocessor to select between external debugging, supported via the physical system interface, and internal debugging, supported via logic within the microprocessor which is controlled by decoded software instructions. In one example of the present invention, a microprocessor includes a system bus interface and a program decoder which is coupled to the system bus interface. The system bus interface is coupled to a system bus to which external memory is coupled. Debugging operations are stored as debugging instructions in the external memory. When these debugging instructions are retrieved from memory, through the system bus and the system bus interface, they are decoded in the program decoder of the microprocessor and they in turn cause the microprocessor to enter a first debugging mode which is controlled by the debugging instructions. The first debugging mode may be referred to as an internal programmable method. The microprocessor also includes a dedicated test port, such as a JTAG port, which provides signals to and from registers and other logic in test port logic on the IC (integrated circuit) of the microprocessor. The dedicated test port includes input/output pins on the microprocessor which convey the test signals to external test logic device, such as JTAG test equipment. Testing of the microprocessor using the dedicated test port involves asserting a signal in the test port which causes the microprocessor to enter a second debugging mode which is controlled by the external test logic device. This second debugging mode may be referred to as an external debug method.

Inventors: Choquette; Jack H. (Los Altos, CA), Smith; Donald W. (Santa Clara, CA)

Assignee: SandCraft, Inc.

International Classification: G06F 11/36 (20060101); G06F 011/00 ()

Expiration Date: 10/30/2018