Patent Number: 6,311,299

Title: Data compression circuit and method for testing embedded memory devices

Abstract: A test circuit enables a memory tester to test for defective memory cellsin a memory portion of an Embedded DRAM or other memory device having arelatively wide internal data path. The Embedded DRAM includes a memoryhaving an array of memory cells, the memory being coupled to a logiccircuit. The test circuit includes at least one external terminal and aplurality of data masking circuits. Each data masking circuit is coupledto a respective one of the arrays and transfers data signals to and fromaddressed memory cells in the array. The data signals are selectivelymasked responsive to a data masking signal. A plurality of datacompression circuits each is coupled to a respective data masking circuitto receive a respective data signal. Each data compression circuitcompares each of the data signals applied on its respective inputs to anexpected value and generates an active error signal on a respectiveexternal terminal responsive to any of the applied data signals not havingthe expected value. When the test mode signal goes active, a test controlcircuit applies addressed data to the data masking circuits. The controlcircuit initially disables the data masking signals so the addressed datais not masked and controls the data compression circuits to generate therespective error signals responsive to the applied data. When at least onethe error signals goes active, the test control signal goes active causingthe test control circuit to control the data masking signals tosequentially mask each data signal applied to the data masking circuitthat generated the active error signal to enable an external tester todetect a defective memory cell from the error signals.

Inventors: Bunker; Layne G. (Boise, ID)


International Classification:

Expiration Date: 10/32013