Patent Number: 6,311,301

Title: System for efficient utilization of multiple test systems

Abstract: A system for efficient utilization of multiple test systems may include an apparatus for testing an electronic circuit board, which comprises a number of computer readable media containing computer readable program code comprising code for a test analysis system that interfaces with at least two test systems. The test analysis system reads a description of said board's board topology and analyzes a number of potential defects of said board based on that description. The test analysis system creates at least two test procedures for the at least two test systems by creating a first test procedure to test the electronic circuit board on a first test system of the at least two test systems. The system then creates at least one other test procedure to test the electronic circuit board on at least one other test system of the at least two test systems. The system then optimizes the at least one other test procedure based on at least one other of the at least two test procedures created for the at least two test systems to reduce redundancies in the at least two test procedures.

Inventors: Posse; Kenneth E. (Fort Collins, CO), Oresjo; Stig (Loveland, CO), Monterio; Patricia (Fort Collins, CO), Dudfield; Anne (Fort Collins, CO)

Assignee:

International Classification: G01R 31/28 (20060101); G06F 011/00 ()

Expiration Date: 10/30/2018