Patent Number: 6,311,302

Title: Method and arrangement for hierarchical control of multiple test access port control modules

Abstract: An arrangement controls an IC designed with multiple "TLM'ed core" circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled a time. For applications typically requiring that control be transferred between such TAP controllers of various core circuits, one embodiment of the present invention expands a multiple "TLM'ed core" circuit design without changing the IEEE JTAG specification and without requiring more scan chains per TAP'ed core. One particular example embodiment includes each of the design's multiple cores including multiple test-access port (TAP) controllers, and including an internal TLM having a TLM register adapted to store a decodable instruction and a supplemental storage circuit adapted to store a coded signal. Also in the design, a chip-level TLM communicates with a common IEEE JTAG interface and with each of the multiple cores via the TLM register and the supplemental storage circuit. The chip-level TLM and the multiple cores signal use the supplemental storage circuit to indicate when instructions are to be transferred from a TLM'ed core to the chip-level TLM.

Inventors: Cassetti; David (Tempe, AZ), Steele; James (Chandler, AZ), Adusumilli; Swaroop (Tempe, AZ)

Assignee: Philips Semiconductor, Inc.

International Classification: G01R 31/28 (20060101); G01R 31/3185 (20060101); G01R 031/28 ()

Expiration Date: 10/30/2018