Patent Number: 6,311,310

Title: Method and apparatus for wiring integrated circuits with multiple power buses based on performance

Abstract: A method and structure for designing a circuit, including identifying paths in the circuit not satisfying a preselected performance criteria, wherein identified paths are initially designed to be coupled to a first power supply, and redesigning the circuit such that the identified paths are coupled to a second power supply having a higher voltage than the first power supply. The higher voltage increases performance of the identified paths such that the identified paths satisfy the performance criteria.

Inventors: Bernstein; Kerry (Underhill, VT), Ellis-Monaghan; John Joseph (Grand Isle, VT), Rohrer; Norman Jay (Underhill, VT)

Assignee: International Business Machines Corporation

International Classification: G06F 17/50 (20060101); G06F 017/50 ()

Expiration Date: 10/30/2018