Patent Number: 6,311,312

Title: Method for modeling a conductive semiconductor substrate

Abstract: A method models conductive regions of a semiconductor substrate in conjunction with conductors in the interconnect structures above the semiconductor substrate. Such a method allows highly accurate extraction of capacitance in planar (e.g., shallow trench isolation) and non-planar (e.g., thermal oxide isolation) semiconductor structures. This method is particularly applicable to modeling dummy diffusion regions prevalent in shallow trench isolation structures. An area-perimeter approach simplifies calculation of capacitance without using a 3-dimensional electric field solver. A method is also provided for extracting a capacitance associate with a contact, or a connecting conductor between two conductor layers.

Inventors: Chang; Keh-Jeng (San Jose, CA), Mathews; Robert G. (Los Altos, CA), Chang; Li-Fu (Santa Clara, CA), Yang; Xu (Sunnyvale, CA)

Assignee: Sequence Design, Inc.

International Classification: G06F 17/50 (20060101); G06F 017/50 ()

Expiration Date: 10/30/2018