Patent Number: 6,311,314

Title: System and method for evaluating the loading of a clock driver

Abstract: The present invention is generally directed to a system and method for evaluating the loading of a clock driver. Specifically, the present invention operates by evaluating a netlist file of a circuit. In accordance with one aspect of the present invention, a method evaluates each node within a netlist file to determine: (1) whether that node is an output node for a clock driver; and (2) for clock driver nodes, whether that node is within loading specification for the particular clock driver circuit. In accordance with one embodiment of the invention, the method operates by identifying a clock driver output node, calculating a PFET: NFET ratio of the clock driver output node, determining a "category" of the clock driver output node, obtaining a load on the clock driver output node, and determining whether the load is within specification for the clock driver circuit. In accordance with the preferred embodiment, the step of identifying a clock driver output node is performed by evaluating a data structure associated with that node. Specifically, in the preferred embodiment a database is created, whereby each node and each element within a netlist file has certain characteristics or attributes that are determined during a preliminary stage of operation, and stored within a data structure for subsequent retrieval and use. One such flag or attribute that is stored for each node is a clock attribute. Any node associated with a clock driver circuit may be readily determined by evaluating this attribute stored within the data structure. This information may be obtained from PathMill or some other similar software package.

Inventors: McBride; John G (Ft Collins, CO)

Assignee: Hewlett-Packard Company

International Classification: G06F 17/50 (20060101); G06F 017/50 ()

Expiration Date: 10/30/2018