Patent Number: 6,311,315

Title: Semiconductor integrated circuit, design method and computer-readable recording medium

Abstract: A first to fifth plugs provide interconnection between each transistor and a first metallic interconnection layer. A sixth to eighth plugs provide interconnection between the first metallic interconnection layer and a second metallic interconnection layer. The total opening area of a connecting window including at least one connecting hole (or the number of connecting holes) is designed in a smaller zone when the type of electric current (waveform) is a bidirectional-directional current, when the flow direction of electric current is from a plug to an interconnection line, when the length of interconnection line is long, or when the width of interconnection line is small. Such arrangement makes it possible to achieve a reduction of the area occupied by interconnections by performing layout design allowing for the permissible electric current amount, without having to prepare complicated tables or without having to perform huge amounts of arithmetic processing. As a result, the interconnection area can be reduced, and fine, high-density semiconductor integrated circuits can be fabricated.

Inventors: Tamaki; Tokuhiko (Osaka, JP)

Assignee: Matsushita Electric Industrial Co., Ltd.

International Classification: G06F 17/50 (20060101); H01L 23/52 (20060101); H01L 21/70 (20060101); H01L 23/522 (20060101); H01L 21/8238 (20060101); H01L 27/02 (20060101); G06F 017/50 ()

Expiration Date: 10/30/2018